The present invention relates to a semiconductor memory device, and particularly to an improvement for a higher integration.
An example of a memory cell organization of a highly integrated dynamic semiconductor memory device as proposed in the 1985 IEEE International Solid-State Circuits Conference at FAM 17.4 is shown in FIGS. 1A and 1B. Specifically, FIG. 1A is a plan view. FIG. 1B is a cross sectional view along IB--IB in FIG. 1A. As illustrated, the memory device comprises a p-type semiconductor substrate 1, a field oxide film 2, a first poly-silicon layer 3, a capacitor insulating (dielectric) film 4, an n.sup.+ diffusion layer 5, a first Al interconnection layer 6 forming bit lines and a second poly-silicon layer 7 forming word lines 9. Although not illustrated as such, the second poly-silicon layer 7 is electrically connected at regular intervals with the second Al interconnection layer 8 to reduce the effective resistance of the word line 9. Contact holes 10 are for electrical connection of the first Al interconnection layer 6 to the n.sup.+ diffusion layer 5. Cp represents a data charge storage capacitance formed of the poly-silicon layer 3 and the n.sup.+ diffusion layer 5 on the rerespective sides of the capacitor insulating film 4, on the sidewall of an isolation trench. Cf represents a data charge storage capacitor formed of the poly-silicon 3 and the n.sup.+ diffusion layer 5 on the respective sides of the capacitor insulating film 4 on the flat part.
By utilizing the sidewall of the isolation trench for forming a data charge storage capacitance Cp, the area for the data charge storage capacitance Cf on the flat part can be reduced. As a result, despite the reduction in the chip area, the operation margin is kept high and the soft error rate is maintained low. With longer periphery of the memory cells, the trench can be made shallower to obtain the same data charge storage capacitance Cp+Cf.
When the memory structure described above is simply combined with the folded-bit line configuration as disclosed in the Japanese Patent Application Laying-open No. 74535/1976, the resultant memory device will have a structure as shown in FIG. 2, which is a cross section along II--II in FIG. 1A.
As illustrated, the first poly-silicon layer 3 must be so patterned (etched) that its edge lies on the bottom of the isolation trench 2. When the isolation trench is made to have the minimum patterning width, etching the poly-silicon layer in such a manner that its edge lies in the bottom of the isolation trench is difficult.
Moreover, there are isolation trenches on both sides of the channel region of the transfer gate controlled by the second poly-silicon layer 7 forming the word line. Leak currents flow through the sidewalls of the isolation trenches, so that the transistor cannot be made completely OFF.